Those of ordinary skill in the field of semiconductor devices will be familiar with many different types of such devices, including, for example, microprocessors and various types of memory devices, such as dynamic random-access memory devices ("DRAMs"), synchronous DRAMs ("SDRAMS"), static random-access memory devices ("SRAMS") capable of storing millions of bits of digital information.
In many cases, semiconductor devices are required to be operated at very high speeds. For example, the clock signal controlling operation of a microprocessor may be a oscillating square wave having a frequency of several hundred megahertz or more, such that the microprocessor is capable of executing hundreds of thousands or even millions of machine instructions each second. Likewise, semiconductor memory devices, whether synchronous or asynchronous, are preferably capable of being accessed (i.e., having data read from or written to) millions of times per second.
A typical semiconductor device operates by being responsive to a plurality of digital control signals applied to its control signal input terminals (often referred to as "pins"). (As used herein, the term "control signal" is intended to refer to essentially any electrical signal applied to a semiconductor device during operation thereof, including without limitation, control signals, clock signals, test signals, address and data signals and the like.) For example, a DRAM device is responsive to a row address strobe ("RAS") input control signal, a column address strobe ("CAS") input control signal, and a read/write ("R/W") signal. To access a memory device, either to read data from a desired location in the memory or to write data to a desired location, external control circuitry manipulates the logic states of the various applied control signals. A RAS signal conditions a memory device to receive a row address applied to its address pins, a CAS signal conditions a memory device to receive a column address applied to its address pins, and the R/W signal conditions the device to perform either a read operation to, or a write operation from, the memory location specified by the received row and column address signals.
A semiconductor device may be responsive to the logic states of control signals, i.e., a logic "1" represented by a control signal having a "high" voltage of 3.3 to 5 volts, or a logic "0" represented by the control signal having a "low" voltage of zero volts. On the other hand, it is not uncommon for a semiconductor device to be responsive to "edges" of certain control signals, i.e., a rising edge transition from a logic "0" state to a logic "1" state, or a falling edge transition from a logic "1" state to a logic "0" state. As a simplified example, a transition from a logic "1" to a logic "0" in the applied RAS control signal, assuming the logic states of certain other applied control signals are appropriate, may define a row address input interval during which time the memory device uses the address bits applied to its address pins to locate the row of memory to be accessed.
Those of ordinary skill in the art will appreciate that when semiconductor devices are to be operated at very fast rates, the timing of the various applied control signals must be very precise. Control signal timing tolerances, typically specified by semiconductor device manufacturers, must be observed in order to ensure proper device operation. Such tolerance parameters are typically defined for each signal relative to one or more other control signals applied to the device. As a generic example, it may be the case that an edge must occur in one signal within a predetermined period of time following the occurrence of an edge in some other applied signal. As another generic example, it may be specified that one particular control signal must be in a given state (high or low) for at least some predetermined period of time prior to the occurrence of an edge in some other signal. Often, these predetermined periods of time are quite small indeed, on the order of one to three nanoseconds, or in some cases even less.
Precision in control signal timing is important not only for the purposes of normal operation of semiconductor devices, but also--perhaps even more so--for the purposes of semiconductor device testing. Precisely controlling and varying control signal timing is important from the standpoint not only of ensuring that a device will operate properly if specified timing parameters are observed, but also of enabling a tester to determine what timing parameters should be specified for a device under test, or to determine to what extent a particular device might be tolerant to control signal timing variations beyond those specified for the device.
One control signal timing issue of particular relevance to the present disclosure arises in connection with performing a particular type of dynamic random access memory access cycle referred to as a read-modify-write cycle. In a read-modify-write cycle, a DRAM memory cell is first accessed to "read" the data stored therein. During a subsequent portion of the read-modify-write cycle, the content of the accessed cell is replaced with new data. As those of ordinary skill in the art will appreciate, during a memory write cycle, it is important for a sufficient voltage to be established on the digit lines while the cell is being accessed, in order to ensure that sufficient charge is stored in the memory cell to enable reliable sensing of the stored data in a subsequent read cycle. Consequently, memory device manufacturers typically specify a minimum time interval for the portion of a read-modify-write cycle in which write-data voltage is established on the appropriate digit lines. After this minimum time interval, referred to as the "write back time," the access transistor for the accessed cell is turned off (i.e., the cell's "row select" line is deasserted), decoupling the accessed cell from the digit lines presenting the write data.
The amount of charge stored in a DRAM memory cell is very small. Accordingly, the circuitry responsible for reading and writing data to DRAM memory cells is especially susceptible to so-called "process variation." Process variation as used herein refers to the variations in operation and performance of semiconductor devices arising from essentially inevitable variations in the size, shape, elemental composition, doping content, resistivity, and the like of the semiconductor structures comprising the operational circuitry.
Process variation can result in measurable differences in the performance of otherwise identical semiconductor parts. As a simple example, the same field-effect transistor (FET) on two discrete semiconductor devices may perform differently as a result of process variation. As a result of process variation, one FET may turn on "harder" than another (i.e., allow more current to flow) in response to the same applied gate voltage. For memory devices, process variation can even lead to variations in the operational behavior from bit to bit within a single device.
The existence of process variation can lead to difficult in specifying minimum operational parameters for semiconductor devices. For example, as a result of process variation, one memory device may operate properly with a particular minimum write-back time interval, while the same write-back time interval may be insufficient in another, identical, device to allow enough charge to be stored in an accessed memory cell.
Although it is possible for a manufacturer to simply specify a minimum write-back interval known to be sufficiently long despite the possibility of process variation, this undesirably prevents the manufacturer from taking advantage of parts tolerant to shorter write-back intervals and hence capable of operating at faster speeds.
Semiconductor device manufacturers typically perform "burn-in" testing and "stress testing" of fabricated parts to verify proper operation within specified timing parameters, as well as to determine whether particular devices might exceed minimum performance criteria and therefore be identified as meeting a higher rating standard. Such testing can also provide the manufacturer with insight into aspects of its design and manufacturing processes, such that such processes can be improved or refined for subsequent generations of parts.
Although there are many benefits to burn-in testing, there are limitations as to what parameters can be manipulated for that purpose. For the most part, the only adjustments that can be made for the purposes of bum-in testing are to the timing of externally applied control signals. There are typically a number of signals present only internally within the semiconductor circuitry, over which external testing equipment can have little or no control as far as timing is concerned.
It is known to provide for a special "test mode" of operation for semiconductor devices. In some cases, the timing of certain signals can be externally manipulated in test mode where they cannot when the device is operated in its normal mode. However, the range of such extra control is typically rather limited.